NED University Journal of Research
ISSN 2304-716X




LVTTL IO STANDARDS AND CAPACITANCE SCALING BASED ENERGY EFFICIENT ALU DESIGN ON FPGA

Author(s): Tanesh Kumar, Pardeep Kumar, Khalil ur Rehman Dayo, Bhawani Shankar Chowdhry, Bishwajeet Pandey

Volume: Special Issue on MCCT'14

Pages: 39 - 47

Date: December 2014

Abstract:
This paper presents the design for an energy efficient 64-bit arithmetic logic unit (ALU) operating in a wide range of frequencies from 125GHz -1THz. Low voltage transistor-transistor logic (LVTTL) input output (IO) standard have been used with different drive strength of 16mA, 12mA, 8mA and 4mA along with capacitance scaling from 25pF to 5pF. It is observed that on scaling down the frequency from 1THz to 125GHz, IO power is reduced up to 87.5%. Similarly, there is a significant reduction in IO power when the capacitance is scaled down from 25pF to 20pF, 15pF, and 10pF, respectively. This design is implemented on 28nm technology based Airtex-7 field programmable gate array (FPGA) device of -1 speed grade. To the best of authorís knowledge, this is the first of its kind of work where an arithmetic logic unit (ALU) has been implemented using LVTTL IO standard.

Full Paper | Close Window      X |